DPControl H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. It currently can encode up to UltraHD 4K in I frame mode (all frames are keyframes): the IP core is smaller but yields less compression. It does not require external memory but only internal BRAM.
The main features of the H.264 Encoders are:
- Compliance Standard: H.264/AVC (ISO/IEC14496-10), Main, Baseline profiles.
- Achieves UltraHD 4K 60 fps on low-end and low-cost Zynq-7000 SoC
- Unlimited resolutions supported, from QVGA to 4K and beyond with the same IP core.
- Very low latency < 1 ms. Only 16 lines from first pixel input to first byte ouput.
- Constant throughput of 3 clk per encoded pixels.
- Realtime configurable Variable Bit Rate (VBR) and Constant Bit Rate (CBR) automatically controls all H.264 parameters.
- Preserves full color fidelity with color subsampling 4:4:4 (4:2:2 and 4:2:0 inputs allowed too).
- Precision: 8 bits or 10 bits
- Output in Byte stream format (raw .264) for easier encapsulation.
- Verilog Source and Netlist versions available
- Pre-packaged for Coregen via IP-XACT
- Entropy Encoding: CAVLC
The input/output interfaces of the H264E IP core are the following:
- Configuration Interface: AXI-Lite slave with a 32 bits interface to control all the necessary parameters of encoding
- Data I/O Interface: AXI4-Stream pixel input interface and AXI4-Stream coded video output. AXI3/4 Master interface with a data width of 64 bits for writing H.264 encoded files from/to memory
- Interrupt outputs: Rising-edge interrupts every encoded frame