Gamma Correction IP
Gamma correction, also known as gamma compression or encoding, is used to encode linear luminance or RGB values to match the non-linear characteristics of display devices. Gamma correction helps to map data into a more perceptually uniform domain, so as to optimize perceptual performance of a limited signal range, such as a limited number of bits in each RGB component.Gamma correction is, in the simplest cases, defined by where the input and output values are between 0 and 1. The case <1 is often called gamma compression and >1 is called gamma expansion.
When used in conjunction with an embedded or external processor, the Gamma Correction core supports frame-by-frame dynamic reprogramming of the gamma tables. The gamma tables can be reprogrammed with arbitrary functions, supporting a wide range of applications, such as intensity correction, feature enhancement, lin-log, log-lin conversion and thresholding.
The Gamma Correction core also offers various configuration options for a designer to optimize the block RAM footprint required by the core. The Gamma Correction core is implemented as a set of LUTs that are used to perform the data transformation. The width of the input data determines the number of entries.
DPC Gamma Correction core uses industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the core. The Figure below illustrates an I/O diagram of the IP. Some signals are optional and not present for all configurations of the core.
Notice how the module requires two clocks for its operation. It is in fact customary that the configuration clock that drives the AXI4-lite configuration bus has lower frequency than the video stream clock. This simplifies the synthesis and placement of the component. The table below summarizes the meaning of every signal.
|Signal / Bus Name||Direction||Description|
|s_axi_BUS_A||Slave||AXI-Lite Bus for the configuration of IP.|
|inter_pix||Slave||AXI4-Stream Bus for input stream.|
|ap_clk||In||Input Clock for streaming domain.|
|ap_rst_n||In||Low reset synchronized with streaming clock.|
|s_axi_clk||In||Input clock for axilite domain.|
|ap_rst_n_s_axi_clk||In||Low reset synchronized with axilite clock.|
|out_pix||Master||AXI4-Stream Bus for output stream.|
|interrupt||Out||Signal indicating the end of the task.|