Color Correction Matrix

 

The Color Correction Matrix IP core provides a method for correcting the image data for these variations. This fundamental block operates on either YUV or RGB data, and processing is “real-time” as a pre-processing hardware block.

The blue color channel is a combination of the blue photons from the scene, multiplied by the relative response of the blue filter, multiplied by the relative response of the silicon to blue photons. However, the filter and silicon responses might be quite different from the response of the human eye, so blue to the sensor is quite different from blue to a human being.
This difference can be corrected and made to more closely match the blue that is acceptable to human vision. The Color Correction Matrix core multiplie s the pixel values by some coefficient to strengthen or weaken it, creating an effective gain. At the same time a mixture of green or red can be added to the blue channel. To express this processing mathematically, the new blue (Bc) is related to the old blue (B), red (R), and green (G) according to:

Bc = K1 x R + K2 x G + K3 x B

where K1, K2, and K3 are the weights for each of the mix of red, green, and blue to the new blue.

If we consider all the channel, we can write

As you can see, you can manage both RGB and YCbCr video streams. The current flow type must be specified in certain register programmed by AXI4-Lite protocol.

 

Interface

DPC Color Correction Matrix core uses industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the core. The Figure below illustrates an I/O diagram of the IP. Some signals are optional and not present for all configurations of the core.

Notice how the module requires two clocks for its operation. It is in fact customary that the configuration clock that drives the AXI4-lite configuration bus has lower frequency than the video stream clock. This simplifies the synthesis and placement of the component. The table below summarizes the meaning of every signal.

Signal / Bus Name Direction Description
s_axi_BUS_A Slave AXI-Lite Bus for the configuration of IP.
inter_pix Slave AXI4-Stream Bus for input stream.
ap_clk In Input Clock for streaming domain.
ap_rst_n In Low reset synchronized with streaming clock.
s_axi_clk In Input clock for axilite domain.
ap_rst_n_s_axi_clk In Low reset synchronized with axilite clock.
out_pix Master AXI4-Stream Bus for output stream.
interrupt Out Signal indicating the end of the task.