Images captured by a CMOS/CCD image sensor are monochrome in nature. To generate a color image, three primary colors – typically Red, Green, and Blue – are required for each pixel. Before the invention of color image sensors, the color image was created by superimposing three identical images with three different primary colors. These images were captured by placing different color filter s in front of the sensor, allowing a certain bandwidth of the visible light to pass through.
Kodak scientist Dr. Bryce Bayer realized that an image sensor with a Color Filter Array (CFA) pattern would allow the reconstruction of all the colors of a scene from a single image capture. On below we have an example of Bayer’s pattern.
The original data for each pixel contains information only about one color, based on which color filter is positioned over that pixel. However, information for all three primary colors is needed at each pixel to reconstruct a color image. Some missing information can be recreated from the information available in neighboring pixels. This process of recreating the missing color information is called color interpolation or demosaicing, and may require dedicated hardware to process the image data in real-time.
The algorithm implemented was proposed by Malvar, He and Cutler in 2004 and is increasingly becoming successful within the scientific community. On below we have an example of demosaicing transformation. On the left we have a monochrome picture where appear only one channel for every pixel. On the left we have the trasformated picture with all interpolated channel for every pixel.
The Color Filter Array (CFA) core uses industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the core. The Figure below illustrates an I/O diagram of the CFA core. Some signals are optional and not present for all configurations of the core.
Notice how the module requires two clocks for its operation. It is in fact customary that the configuration clock that drives the AXI4-lite configuration bus has lower frequency than the video stream clock. This simplifies the synthesis and placement of the component. The table below summarizes the meaning of every signal.
|Signal / Bus Name||Direction||Description|
|s_axi_BUS_A||Slave||AXI-Lite Bus for the configuration of IP.|
|inter_pix||Slave||AXI4-Stream Bus for input stream.|
|ap_clk||In||Input Clock for streaming domain.|
|ap_rst_n||In||Low reset synchronized with streaming clock.|
|s_axi_clk||In||Input clock for axilite domain.|
|ap_rst_n_s_axi_clk||In||Low reset synchronized with axilite clock.|
|out_pix||Master||AXI4-Stream Bus for output stream.|
|interrupt||Out||Signal indicating the end of the task.|