Defective Pixel Correction


An image sensor may have a certain number of defective pixels that may be the result of manufacturing faults, failures during normal operation, or variations in pixel voltage levels based on temperature or exposure. A wide class of pixel defects may be characterized as: dead (always low), hot (always high), or stuck (to a certain value). These anomalies can further be characterized as static (always present) or dynamic (as a function of exposure or temperature).


The Defective Pixel Correction is the module that takes care of eliminating these anomalies from the Video in input stream. The module for each pixel identifies a 5×5 ROI of adjacent pixels and calculates an estimate of the pixel of interest. The estimate can be substituted for the real pixel if the difference between the two exceeds a certain threshold, which acts as a parameter to the module.

The simplicity of the algorithm ensures excellent visual performance, in addition to the high frequencies of execution and the low occupations found on Xilinx® devices Zynq®-7000 AP SoC, 7 Series and newer FPGAs.



The Defective Pixel Correction (DPC) core uses industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the core. The Figure below illustrates an I/O diagram of the DPC core. Some signals are optional and not present for all configurations of the core.

Notice how the module requires two clocks for its operation. It is in fact customary that the configuration clock that drives the AXI4-lite configuration bus has lower frequency than the video stream clock. This simplifies the synthesis and placement of the component. The table below summarizes the meaning of every signal.

Signal / Bus Name Direction Description
s_axi_BUS_A Slave AXI-Lite Bus for the configuration of IP.
inter_pix Slave AXI4-Stream Bus for input stream.
ap_clk In Input Clock for streaming domain.
ap_rst_n In Low reset synchronized with streaming clock.
s_axi_clk In Input clock for axilite domain.
ap_rst_n_s_axi_clk In Low reset synchronized with axilite clock.
out_pix Master AXI4-Stream Bus for output stream.
interrupt Out Signal indicating the end of the task.