Key Features:
  • ISP module streaming is AXI4-Stream compliant
  • Support for 8/10/12 bit depth input
  • ISP module are AXI4-Lite compliant for configuration
  • Supports resolutions up to 7680×7680, including 4K2Kp30 (3840×2160)
  • Very small area required on Xilinx 7-series and newer FPGAs


The image Signal Processing Pipeline proposed by DPControl is designed for video processing and video enhancement of embedded design based on Xilinx Programmable Devices. Each module has been implemented respecting the compatibility with the AMBA AXI4 standards, making the entire architecture completely configurable and versatile. The ISP accepts in input a video stream with 8 or 10 or 12 bits depth. The Defective Correction module takes care of eliminating the Salt-Pepper error. The Color Filter Array is an implementation of the Malvar-Cutler algorithm, widely appreciated in literature and increasingly requested in the vision world. Statistics on the video stream are captured for possible adaptive control algorithms and applied color and gamma corrections. Color conversion in YUV space with color sub-sampling 4:2:2 or 4:2:0 is supported.


The Image Signal Processing Pipeline IP core is prepackaged for Xilinx Vivado IP Integrator (IPI) tool, requires no skills beyond general tools knowledge and can be used in same ways as Xilinx IP cores. The Architecture is completely configurable to switching on and off pipeline stages (blocks) and setting up all IP core’s parameters through AXI4-Lite Interface.